CACHE AWARE DATA LAYOUTS
Department of Statistics and Computer Science
University of Colombo
Colombo, Sri Lanka
Feeding the CPU with data operands is the bottleneck in many scientific computations. This bottleneck is alleviated by means of caches, small fast memories to keep data. The performance of a memory-intensive computation depends critically on whether most of the data accesses can be performed within the cache. This research is on cache aware computing, in which the programmers make their code cache friendly. In particular, we have tested cache aware data laying which is a promising technique as it gives significant performance improvements. For example, we recorded an improvement of about 64% over the standard matrix multiplication.