Traditional VLSI circuit simulation is based on the numerical solution of large-scale stiff nonlinear systems of differential-algebraic equations (DAEs). Numerical techniques for such DAEs require the repeated solution of large sparse systems of linear equations, and iterative methods, such as Krylov-subspace algorithms, seem to be predestined to the solution of these linear systems. However, for various reasons, standard SPICE-like circuit simulators employ direct methods, rather than iterative methods. Nevertheless, the continuing evolution of VLSI circuits has now come to a point where Krylov-subspace methods are finally becoming mainstream tools in circuit simulation. More precisely, today, Krylov-subspace iterations are employed to generate reduced-order models of large linear subsystems of DAEs that describe large linear subcircuits of the VLSI circuit to be simulated.
In this talk, we explain why and how Krylov-subspace methods are used for reduced-order modeling in VLSI circuit simulation. We discuss various desirable and in part conflicting properties of the reduced-order models, such as high approximation accuracy, stability, and passivity, and show how to achieve these properties by means of Krylov-subspace iterations. Numerical results for a variety of circuit examples are presented.